Ac Coupling And Gate Charge Pumping For Nmos And Pmos Device Control

ABSTRACT

An AC electrically coupled FET device ( 301 ) is disclosed with a coupling capacitor ( 302 ) disposed for receiving a digital input signal having transitions and for AC coupling this input signal to the gate terminal of the FET device ( 301 ). A reference bias circuit ( 306 ) is provided for providing a first bias voltage ( 403   b ) that is above a threshold voltage of the FET device ( 301 ) and a second bias voltage ( 403   a ), where the first and second bias voltage ( 403   b,    403   a ) are higher than rail to rail supply voltages. Switching circuitry ( 304, 305 ) is electrically coupled with the gate terminal of the FET device ( 301 ) for one of coupling of the first bias voltage ( 403   b ) and uncoupling of the second bias voltage ( 403   a ) and coupling of the second bias voltage ( 403   a ) and uncoupling of the first bias voltage ( 403   b ) in response to the transitions in the digital input signal.

The invention relates to the field of controlling of field effect transistor (FET) devices and more specifically to the field of controlling a gate terminal of the FET device using charge pumping.

In many digital circuits, field effect transistor (FET) devices are used in order to control propagation of electrical signals. These FET devices are typically fabricated using PMOS or NMOS processes. Control of these FET devices is achieved by varying of a potential that is applied to the gate terminal thereof. Typically, for a FET disposed between two electrical power rails, the potential that is applied to the gate terminal varies between these two rails in order to control propagation of current between the drain and source terminals thereof.

FET devices do not significantly begin to conduct current between their drain and source terminals until a threshold voltage (Vt) for the device is reached, and surpassed. Thus, for a rising potential provided to the gate terminal of the FET, the FET does not conduct until the rising potential surpasses Vt for the FET device. Similarly, for a falling signal that is applied to the gate terminal of the FET device, the FET does not significantly cease to conduct current until the potential on the gate terminal drops below Vt. Thus, in either case, a delay is experience by the FET device because it doesn't respond with the same speed as the signal on it's gate terminal.

A solution to this problem is to drive the gate terminal of the FET with a bracketed voltage that is higher than the rail-to-rail voltage. Typically, various analog circuits are used in the art, which are known to consume large quantities of electrical power. These circuits, range from generating upper and lower supply voltages for the bracketed gate voltage using resistor divider networks and other forms of feedback loops, and so forth. These techniques work well for low speed switching environments, but lack the performance in maintaining of the transition edge in high-speed applications. These circuits typically present a strong pole at desired high speeds, which means rise and fall edges of digital signals tend to degrade and slow down at high speeds, which is undesirable.

A need therefore exists to provide a potential to a gate terminal of a FET device that is between two different potentials that are not rail-to-rail but are both higher than the rail-to-rail potentials. It is therefore an object of the invention to provide potentials to the gate terminal of a FET device that are not confined to a boundary of a rail-to-rail supply voltage. It is a further object of the invention to reduce electrical power consumption and to enhance performance of these FET devices in switching applications for high-speed circuits.

In accordance with the invention there is provided a circuit comprising: a first supply voltage port for receiving of a first potential; a second supply voltage port for receiving of a second potential that is lower than the first potential; an input port for receiving of a digital input signal having transitions between the first and second potentials; a FET device comprising a gate terminal having a threshold voltage and drain and source terminals electrically coupled between the first and second supply voltage ports; a coupling capacitor disposed between the input port and the gate terminal of the FET device, the coupling capacitor for AC coupling of the digital input signal to the gate terminal of the FET device and for forming a capacitor divider circuit with a capacitor formed at the gate terminal of the FET device; a reference bias circuit comprising a first bias port for providing a first bias voltage that is above the threshold voltage and at least one of the first potential and a potential higher than the first potential and a second bias port for providing a second bias voltage that is higher than the second potential and below the threshold voltage; and, switching circuitry for one of coupling of the first bias voltage and uncoupling of the second bias voltage and coupling of the second bias voltage and uncoupling of the first bias voltage to the gate terminal of the FET device in response to the transitions in the digital input signal.

In accordance with the invention there is provided a method of controlling a gate potential of a FET device comprising: providing a FET device having a threshold voltage and a gate terminal; providing of a first voltage level; providing of a second voltage level that is below that of the first voltage level; providing of a digital input signal having transient switching between approximately the first voltage level and approximately the second voltage level; capacitively coupling of the digital input signal to the gate terminal of the FET device; providing a first bias voltage that is at least at a potential of the first voltage level and higher than the potential of first voltage level, where the first voltage level is at a higher potential than the second voltage level; providing a second bias voltage that is higher than the second voltage level; determining whether the digital input signal is one of rising from the first voltage level to the second voltage level and falling from the second voltage level to the first voltage level; and, electrically coupling one of the first bias voltage and electrically uncoupling of the second bias voltage and electrically coupling of the second bias voltage and electrically uncoupling of the first bias voltage to the gate terminal of the FET device in response to the respective rising and falling of the digital input signal in dependence upon the determination.

In accordance with the invention there is provided a storage medium for storing of instruction data comprising: first instruction data for providing a FET device having a threshold voltage and a gate terminal; second instruction data for providing of a first voltage level; third instruction data for providing of a second voltage level that is below that of the first voltage level; fourth instruction data for providing of a digital input signal having transient switching between approximately the first voltage level and approximately the second voltage level; fifth instruction data for capacitively coupling of the digital input signal to the gate terminal of the FET device; sixth instruction data for providing a first bias voltage that is at least at a potential of the first voltage level and higher than the potential of first voltage level, where the first voltage level is at a higher potential than the second voltage level; seventh instruction data for providing a second bias voltage that is higher than the second voltage level; eighth instruction data for determining whether the digital input signal is one of rising from the first voltage level to the second voltage level and falling from the second voltage level to the first voltage level; and, ninth instruction data for electrically coupling one of the first bias voltage and electrically uncoupling of the second bias voltage and electrically coupling of the second bias voltage and electrically uncoupling of the first bias voltage to the gate terminal of the FET device in response to the respective rising and falling of the digital input signal in dependence upon the determination.

Exemplary embodiments of the invention will now be described in conjunction with the following drawings, in which:

FIG. 1 illustrates a typical NMOS device;

FIG. 2 a illustrates a coupling capacitor (Cc) that is disposed between a predriver circuit and the gate terminal of a field effect transistor (FET) device;

FIG. 2 b illustrates a portion of the circuit shown in FIG. 2 a, where a first voltage source provides a potential of VG through the Cc to the gate terminal of the FET device;

FIG. 3 illustrates a preferred embodiment of the invention, a DC restoration circuit, which addresses both issues of charge leakage and maintaining of the gate potential of a FET device within predetermined first and second potential limits; and,

FIG. 4 illustrates operation of the circuit shown in FIG. 3 during a transient switching operation.

FIG. 1 illustrates a NMOS device 101 having a threshold voltage (Vt) with first voltage source 111 having a potential of VG electrically coupled to the gate terminal of the NMOS device 101. A second voltage source 112 is electrically coupled to its source terminal and has a potential of VS. A third voltage source 113 is electrically coupled to its drain terminal and has a potential of VD. The potentials, VG, VS and VD are all relative to a common ground terminal 100 b electrically coupled with each of the voltage sources, 111, 112 and 113. A potential Vg is a potential on the gate terminal of the FET device 101 and VG is a potential of a voltage source that is applied to the gate terminal.

In operation of the NMOS device 101 shown in FIG. 1, the device does not conduct current from its drain to source terminals when Vg=<VS. Once VS<Vg<VG+Vt, where Vt is the threshold voltage of the NMOS device 101, the device 101 starts to conduct current from its drain to source terminals. The device 101 conducts more current when Vg>=VS+Vt and conducts maximum current when Vg>VD+Vt.

When the potential Vg is rising from the ground potential hardly any current flows until Vg is reached for the NMOS device 101, where VS<Vg<VG+Vt. For the NMOS device 101 to conduct substantial current, VG is higher, such as when VG>=VS+Vt and when Vg>VD+Vt. If Vg is a rail to rail signal (Vdd), and VS is ¼ Vdd, this translates into an at least 25% waste in the rising or falling edges of the gate voltage Vg, which means slower NMOS device 101 performance. Since for more than 25% of the time, the NMOS device 101 is off. If the potential Vg does not increase to VD+Vt, the speed performance of the NMOS device 101 degrades substantially.

Thus, a need exists for a bracketed gate voltage that is a fraction of the supply voltage, which has minimum voltages that is greater that the ground potential (0V) and a maximum voltage that is at least the potential of the supply voltage or greater. Of course, similar reasoning is also contemplated for a PMOS device.

A series capacitor is typically used to couple an AC, or transient, signal between a signal source and a load. These types of capacitors block any DC current form flowing between the signal source and the load. Furthermore, the series capacitor is a high fidelity medium for propagating of high-speed signals since it doesn't degrade the signal and preserves signal edges for digital signals. Because of these two known capacitor characteristics, and since the gate terminal of PMOS and NMOS devices is a capacitor, a capacitor voltage divider circuit is constructed, as illustrated in FIGS. 2 a and 2 b. This capacitor voltage divider is used to create the desired gate voltage bracket, or the fractional gate voltage, that is used for improved NMOS or PMOS FET device performance.

FIG. 2 a illustrates a coupling capacitor (Cc) 202 that is disposed between a predriver circuit 203 and the gate terminal of a field effect transistor (FET) device 201, in this example the FET device 201 is in the form of a NMOS FET. Electrically coupled to the source terminal of the FET device 201 is a second voltage source 212 with a potential of VS. Electrically coupled to the drain terminal of the FET device 201 is a third voltage source 213 with a potential of VD. The potentials VS and VD are all relative to a second supply voltage port, which is a common ground terminal 200 b electrically coupled with each of the voltage sources 212 and 213. A first supply voltage port is electrically coupled with each of the voltage sources, 213 and 212, and the predriver circuit 203 for providing of a positive supply voltage thereto (Vdd).

FIG. 2 b illustrates a portion of the circuit shown in FIG. 2 a, where a first voltage source 211 provides a potential of VG through the Cc 202 to the gate terminal of the FET device 101, which is a gate capacitor Cg 201 a. The potential on the gate terminal (Vg) of the FET device 201 is:

Vg=VG*(Cc/(Cc+Cg)

or

Cc=Vg*Cg*(VG−Vg)

Thus, for a very large value Cc, Cc=>Vg=VG and if Cc=Cg=>Vg=VG/2. Therefore, when the Cc is used in CMOS environment with a FET device, such as a NMOS or a PMOS FET, provides a capacitor divider configuration in order to provide the voltage-swing for the bracketed gate voltage.

Preferably, these coupling capacitors are MOS capacitors, which are typically manufactures as NMOS in Nwell devices, which share a same NMOS or PMOS FET gate characteristic. Therefore, the capacitor divider is a geometrical ratio of CMOS FET devices to a first order. Because of the first order, this facilitates generation of the voltage swing for the bracketed gate voltage.

However, in order for AC coupling to be implemented, there are two issues: charge leakage and level shifting of the gate voltage for the FET device to predetermined voltage levels. During long period of inactivity, the gate charge on the gate capacitor 201 a that forms the gate terminal of the FET device 201 is known to leak and this results in a depletion of electrical potential on the gate terminal. AC coupling by itself provides a voltage ratio, but in order to provide a gate potential that is within predetermined upper and lower limits, additional circuitry is used, such as a charge pump, in order to charge the gate terminal to the predetermined voltage levels.

FIG. 3 illustrates a preferred embodiment of the invention, a DC restoration circuit 300, which addresses both issues of charge leakage and maintaining of the gate potential of a FET device 301 within predetermined first and second potential limits, which are preferably upper and lower potential limits for the bracketed gate voltage. The DC restoration circuit 300 includes a coupling capacitor (Cc) 302 that is disposed between an output port of a predriver circuit 303 and a first junction 301 b that is electrically coupled with the gate terminal of the FET device 301, in the form of a NMOS FET device. Electrically coupled to the source terminal of the FET device 301 is a second voltage source 312 with a potential of VS. Electrically coupled to the drain terminal of the FET device 301 is a third voltage source 313 with a potential of VD. The potentials VS and VD are all relative to a second supply voltage port 300 b, which is a common ground terminal, electrically coupled with each of the voltage sources 312 and 313. A first supply voltage port 300 a is electrically coupled with each of the voltage sources, 313 and 312 for providing of a positive supply voltage thereto (Vdd). The predriver circuit 303 also includes an input port 300 c for receiving of a digital input signal and is disposed between the first supply voltage port 300 a and the second supply voltage port 300 b.

In order to prevent leakage of current from the gate terminal of the FET device 301, during long periods of inactivity, switching circuitry is used. The switching circuitry includes a first switch 304 and a second switch 305 electrically coupled with the first junction 301 b and the gate terminal of the FET device 310. The first switch 304, in the form of an integrated CMOS switch, is disposed between a first bias port 300 d and the first junction 301 b. A second switch 305, in the form of an integrated CMOS switch, is disposed between a second bias port 300 e and the first junction 301 b. A control circuit 307 is used to control each of the switches, 304 and 305, for opening and closing thereof. Preferably a potential of the third voltage port 300 d is higher than that of the fourth voltage port 300 e.

The potentials on the first and second bias ports, 300 d and 300 e, are generated by a low power reference bias circuit 306. The reference bias circuit 306 is either in the form of a charge pump circuit, or the reference bias voltages are provide by a high voltage source. The voltage swing is predetermined by the Cc 302 and Cg 301 a ratio during design of the circuitry 300.

In use, the first switch 304, or the upper switch, is used for providing of the first bias voltage to the gate terminal of the FET device 301 in order to restore the DC voltage on the gate terminal of the FET device 301 with an upper voltage limit when the gate terminal is provided with a logic HIGH signal. The second switch 305, or lower switch, is used for providing of a second bias voltage to the gate terminal of the FET device 301 for discharging of the gate terminal of the FET device 301 when the gate terminal is provided with a logic LOW signal.

Referring to FIG. 4, in operation of the circuit shown in FIG. 3, during a transient switching operation, when the digital input signal 402 provided to the input port 300 c is rising or falling, the following occurs. As the potential of the input signal 402 rises from approximately 0V to Vdd, the control circuit 307 turns off the second switch 305 and turns on the first switch 304. This operation results in electrically coupling of the gate terminal of the FET device 301 to the first bias port 300 d, which provide the first bias voltage 403 b to the gate terminal of the FET device 301. As the potential of the input signal 402 falls from Vdd to approximately 0v, the control circuit 307 turns off the first switch 304 and turns on the second switch 305. This operation then couples the gate terminal of the FET device 301 with the second bias port 300 e, which provides the second bias voltage 403 a to the gate terminal of the FET device 301. The bracket voltage 401 is realized between the first and second bias voltages, 403 b and 403 a.

Referring to FIG. 4, example waveforms for DC restoration and charge pumping for the circuit 300 are shown. Because the first and second switches, 304 and 305, are only used in order to maintain a gate potential on the gate terminal of the CMOS device 301 they are small integrated devices since they propagate minimal current. Because they are small devices, they do not significantly impact the performance of the FET device 301. Additionally, the bias voltages provided to the first and second bias ports, 300 d and 300 e, have minimal current and thus the low power reference bias circuit 306 consumes minimal electrical power.

Advantageously, the embodiment of the invention utilizes a Cc electrically coupled with the gate terminal of the FET device 301 to AC couple an input signal to the gate terminal. The gate terminal and Cc act as a subsequent stage. Because of AC coupling and because of the switching circuitry, the bracketed gate voltage is provided by the capacitor divider circuit, which is formed from the Cc 302 and the Cg 301 a. Since the Cc 302 is transparent and acts as an AC short for propagating an alternating signal with fast transitions, the capacitor divider structure provides added performance to the operation of the circuit 300.

Advantageously, because the embodiment of the invention utilizes a capacitor ratio between the Cc and the Cg, it results in repeatable and predictable behavior for the circuit 300 that is relatively process independent and is thus implementable in a semiconductor substrate using a CMOS process.

Numerous other embodiments may be envisaged without departing from the spirit or scope of the invention. 

1. A circuit comprising: a first supply voltage port for receiving of a first potential; a second supply voltage port for receiving of a second potential that is lower than the first potential; an input port for receiving of a digital input signal having transitions between the first and second potentials; a FET device comprising a gate terminal having a threshold voltage and drain and source terminals electrically coupled between the first supply voltage port and the second supply voltage port; a coupling capacitor disposed between the input port and the gate terminal of the FET device, the coupling capacitor for AC coupling of the digital input signal to the gate terminal of the FET device and for forming a capacitor divider circuit with a capacitor formed at the gate terminal of the FET device; a reference bias circuit comprising a first bias port for providing a first bias voltage that is above the threshold voltage and at least one of the first potential and a potential higher than the first potential and a second bias port for providing a second bias voltage that is higher than the second potential and below the threshold voltage; and, switching circuitry for one of coupling of the first bias voltage and uncoupling of the second bias voltage and coupling of the second bias voltage and uncoupling of the first bias voltage to the gate terminal of the FET device in response to the transitions in the digital input signal.
 2. A circuit according to claim 1 wherein a potential difference between the first bias voltage and the second bias voltage is smaller than a potential difference between the first potential and the second potential.
 3. A circuit according to claim 1 wherein the switching circuitry comprises: a first switching circuit disposed between the gate terminal of the FET device and the first bias port; and, a second switching circuit disposed between the gate terminal of the FET device and the second bias port.
 4. A circuit according to claim 3 comprising a same semiconductor substrate, where the first switching circuit and the second switching circuit are integrated on the same semiconductor substrate with the FET device and the coupling capacitor.
 5. A circuit according to claim 3 comprising: a control circuit electrically coupled with the first switching circuit and the second switching circuit for closing the first switch and opening of the second switch when the digital signal transitions from approximately the second potential to approximately the first potential, where closing of the first switch results in providing the gate terminal of the FET device with the first bias voltage.
 6. A circuit according to claim 3 comprising: a control circuit electrically coupled with the first switching circuit and the second switching circuit for opening of the first switch and closing of the second switch when the digital signal transitions from approximately the first potential to approximately the second potential, where closing of the second switch results in providing the gate terminal of the FET device with the second bias voltage.
 7. A circuit according to claim 1 wherein the FET device comprises a gate capacitor having a gate capacitance and the coupling capacitor comprises a coupling capacitance, where the gate capacitor and the coupling capacitor form a capacitor divider circuit and where the coupling capacitance is a ratioed factor of the gate capacitance and is one of larger and smaller than the gate capacitance.
 8. A circuit according to claim 1 comprising a same semiconductor substrate, wherein the FET device, the coupling capacitor, the reference bias circuit and the switching circuitry are integrated within the same semiconductor substrate.
 9. A circuit according to claim 1 wherein the reference bias circuit comprises charge pump circuitry for generating of a bracketed gate voltage for provision to the gate terminal of the FET device, wherein the bracketed gate voltage is formed between the first bias voltage and the second bias voltage, wherein the first potential falls within the bracketed gate voltage and the second potential falls below the bracket gate voltage.
 10. A circuit according to claim 1 wherein the reference bias circuit comprises a high voltage source for generating of a bracketed gate voltage for provision to the gate terminal of the FET device, wherein the bracketed gate voltage is formed between the first bias voltage and the second bias voltage wherein the first potential falls within the bracketed gate voltage and the second potential falls below the bracket gate voltage.
 11. A circuit according to claim 1 comprising a predriver circuit having an input port and an output port electrically coupled with the input port, the predriver circuit for receiving of the input signal and for providing this input signal to the coupling capacitor.
 12. A method of controlling a gate potential of a FET device comprising: providing a FET device having a threshold voltage and a gate terminal; providing of a first voltage level; providing of a second voltage level that is below that of the first voltage level; providing of a digital input signal having transient switching between approximately the first voltage level and approximately the second voltage level; capacitively coupling of the digital input signal to the gate terminal of the FET device; providing a first bias voltage that is at least at a potential of the first voltage level and higher than the potential of first voltage level, where the first voltage level is at a higher potential than the second voltage level; providing a second bias voltage that is higher than the second voltage level; determining whether the digital input signal is one of rising from the first voltage level to the second voltage level and falling from the second voltage level to the first voltage level; and, electrically coupling one of the first bias voltage and electrically uncoupling of the second bias voltage and electrically coupling of the second bias voltage and electrically uncoupling of the first bias voltage to the gate terminal of the FET device in response to the respective rising and falling of the digital input signal in dependence upon the determination.
 13. A method according to claim 12 wherein a potential difference between the first bias voltage and the second bias voltage is smaller than a potential difference between the first voltage level and the second voltage level.
 14. A method according to claim 12 wherein the second bias voltage is one of below that of a threshold voltage for the FET device and above that of the threshold voltage for the FET device.
 15. A method according to claim 12, wherein when the digital input signal is rising, coupling of the first bias voltage to the gate terminal of the FET device and other than coupling of the second bias voltage to the gate terminal of the FET device.
 16. A method according to claim 15 comprising increasing a potential of the gate terminal of the FET device to a potential that is higher than that of the first voltage level.
 17. A method according to claim 12 comprising increasing a potential of the gate terminal of the FET device to a potential that is higher than the threshold voltage of the FET device.
 18. A method according to claim 12, wherein when the digital input signal is falling, coupling of the second bias voltage to the gate terminal of the FET device and other than coupling of the first bias voltage to the gate terminal of the FET device.
 19. A method according to claim 18 comprising increasing a potential of the gate terminal of the FET device to a potential that is higher than that of the second voltage level.
 20. A method according to claim 12 wherein, in use, of the FET device the potential on the gate terminal of the FET device transitions between the first bias voltage and the second bias voltage and other than drops to below that of the second bias voltage.
 21. A method according to claim 12 wherein the FET device is one of manufactured using an NMOS and a PMOS process.
 22. A method according to claim 12 comprising providing a capacitor for the capacitive coupling, wherein the capacitor does not discharge to the second voltage level.
 23. A storage medium for storing of instruction data comprising: first instruction data for providing a FET device having a threshold voltage and a gate terminal; second instruction data for providing of a first voltage level; third instruction data for providing of a second voltage level that is below that of the first voltage level; fourth instruction data for providing of a digital input signal having transient switching between approximately the first voltage level and approximately the second voltage level; fifth instruction data for capacitively coupling of the digital input signal to the gate terminal of the FET device; sixth instruction data for providing a first bias voltage that is at least at a potential of the first voltage level and higher than the potential of first voltage level, where the first voltage level is at a higher potential than the second voltage level; seventh instruction data for providing a second bias voltage that is higher than the second voltage level; eighth instruction data for determining whether the digital input signal is one of rising from the first voltage level to the second voltage level and falling from the second voltage level to the first voltage level; and, ninth instruction data for electrically coupling one of the first bias voltage and electrically uncoupling of the second bias voltage and electrically coupling of the second bias voltage and electrically uncoupling of the first bias voltage to the gate terminal of the FET device in response to the respective rising and falling of the digital input signal in dependence upon the determination. 